List of Messages |
CAUSE: The attempt to generate a symbol for a VHDL Design File (.vhd) is unsuccessful, as the design's interface contains a reference to a constant ID. Such an interface is not supported by symbol generation. In symbol generation, only those cases where you specify variables using generics are supported. For example, if a user wants to specify an array with variable width, and still wants to create a symbol for the design entity, you should use generics to specify the boundaries, rather than use VHDL constants to specify array boundaries. This is because VHDL constants will not be included in the generated symbol file, therefore you cannot find the actual value of the boundaries.
ACTION: Replace the VHDL Design File constants with generics, and re-generate the symbol.
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