List of Messages |
CAUSE: In an association list at the specified location in a VHDL Design File (.vhd), you partially associated the specified formal; however, you already associated one or more elements of the formal in a previous partial association. The VHDL language does not allow partial associations to overlap.
ACTION: Review the partial associations for the specified formal and remove any overlap.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.