List of Messages |
my_dff : PROCESS (clk, rst) BEGIN IF rst = '1' THEN q <= '0'; ELSIF clk'EVENT THEN q <= data; END IF; END PROCESS;The Process Statement containing the If Statement may be attempting to create a register that is sensitive to both the positive and negative edges of clk. However, Quartus Prime Integrated Synthesis cannot generate logic to implement a dual-edge register in a device.
my_dff : PROCESS (clk, rst) BEGIN IF rst = '1' THEN q <= '0'; ELSIF clk'EVENT and clk = '1' THEN q <= data; END IF; END PROCESS;
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