List of Messages |
CAUSE: In a Signal Assignment Statement, Variable Assignment Statement, Subtype Declaration, Type Declaration, or generic Interface List at the specified location in a VHDL Design File (.vhd), you used an integer literal for the specified type. However, you cannot use integer literals for the specified type. If this error occurs in a generic Interface List, you may have used the integer literal as an actual in an Association List for a formal in a VHDL entity or an entity in another source language.
ACTION: Remove the integer literal from the assignment, declaration, or Association List, or change the type to one that allows integer literals.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.