List of Messages |
CAUSE: In an expression at the specified location in a VHDL Design File (.vhd), you attempted to specify an enable condition for a clock edge. However, Quartus Prime Integrated Synthesis cannot infer a register to implement the clock enable condition because you attempted to specify the clock enable condition using the specified binary operator, which is not AND. You must combine a clock edge and an enable signal only with a binary AND.
PROCESS (clk) BEGIN IF(rising_edge(clk) AND enable) THEN q <= data; END IF; END PROCESS;
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