List of Messages |
CAUSE: In a VHDL Design File (.vhd) at the specified location, you used a guarded Signal Assignment Statement outside a guarded Block Statement. However, you must use guarded Signal Assignment Statements only in guarded Block Statements.
ACTION: Remove the guarded Signal Assignment Statement, or move the guarded Signal Assignment Statement into a guarded Block Statement.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.