List of Messages |
PROCESS (clk1, clk2) BEGIN IF(rising_edge(clk1) OR rising_edge(clk2)) THEN q <= data; END IF; END PROCESS;This message can occur when you attempt to infer an edge-controlled register that is sensitive to two or more clock edges. However, the Quartus Prime cannot infer a register that is controlled by more than one clock.
ACTION: Change the expression so it uses only one clock edge, that is, so the expression infers an edge-controlled register that is sensitive to only one clock edge.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.