List of Messages |
CAUSE: In a Case Statement at the specified location in a VHDL Design File (.vhd), you specified a Case Statement expression with the specified type. However, the expression must have a discrete type or a one-dimensional array type that has an element base type that is a character type. This error may occur when using a Case Statement to implement RAM in a design.
ACTION: Change the Case Statement using temporary variables and nested Case Statements.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.