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LIBRARY ieee; USE ieee.std_logic_1164.all; entity convert4 is Port ( o : OUT STD_LOGIC ); END convert4; ARCHITECTURE rtl OF convert4 IS component vlg_param Generic ( p1 : boolean := false ); Port ( o : OUT STD_LOGIC ); end component; begin inst1 : vlg_param; end rtl;And the Verilog module that receives the Boolean parameter:
module vlg_param(output o); parameter p1 = 1; endmodule
ACTION: Do not pass unsupported value types to Verilog.
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