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CAUSE: In a Verilog Design File (.v) at the specified location, you used a pullup or pulldown primitive. However, the pullup and pulldown gates are not supported for Quartus Prime Integrated Synthesis, because resistive pullup and pulldown primitives cannot be implemented in Altera devices, except as part of a tri-state driver driving a bidirectional pin.
if (enable == 1'b1) tri_out <= my_sig; else tri_out <= 1'bz;For all other cases, edit the design to use only logic value 1 and logic value 0.
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