List of Messages |
CAUSE: In an Event Control at the specified location in a Verilog Design File (.v), you specified an Event Control that contains both double-edge events and single-edge events. A double-edge event is a signal that is sensitive to both positive and negative edges, for example, always @(A), and usually represents combinational logic. A single-edge event is a signal that is sensitive to just one edge, for example always @(posedge B), and usually represents sequential logic (logic with clocked registers). You cannot include both event types in one Event Control.
ACTION: Change the type of events in the Event Control to be all single-edge or all double-edge events, or split the Event Control into multiple statements.
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