List of Messages |
CAUSE: In a Defparam Statement at the specified location in a Verilog Design File (.v), you used the specified identifier to specify a parameter value for a Module Instance. However, Quartus Prime Integrated Synthesis could not match the identifier to a specific parameter on an instance in the current module. As a result, the defparam identifier was ignored.
ACTION: Check the spelling of the identifier. If it is a hierarchical identifier, verify that it specifies the correct path to a parameter on an instance in the current module.
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