List of Messages |
CAUSE: In an Always Construct, at the specified location in a Verilog Design File (.v), you used a Procedural Continuous Assignment Statement to specify an assignment to a register. However, although the Procedural Continuous Assignment Statement, which overrides a regular assignment, is supported in Verilog HDL, it is not supported in the Quartus Prime software.
ACTION: Either remove the Procedural Continuous Assignment Statement, or try to merge the assignment into other Always Constructs that contain assignments to the same register, by using an If Statement to specify the assignment conditions instead of using a Procedural Continuous Assignment Statement.
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