List of Messages |
CAUSE: In a user-defined primitive (UDP) declaration at the specified location in a Verilog Design File (.v), you did not specify or declare an output as the first port in the port list. A UDP must have a single output port, and the output port must be listed first in the port list.
ACTION: Specify or declare an output port as the first entry in the UDP port list.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.