List of Messages |
CAUSE: In a Verilog Design File (.v) or SystemVerilog Design File (.sv), you referred to an object with a name. However, the name matches an object in the current scope that does not have the correct type for the current context. For example, the name should refer to a module but matches a declared variable.
ACTION: Modify the name to match the correct object, or remove the conflicting declaration from the current scope.
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