List of Messages |
CAUSE: At the specified location in a Verilog Design File (.v), you used a loop that did not terminate within the specified number of iterations. That is, the terminating condition for the loop was never false within the iteration limit. To avoid a potential infinite loop or memory exhaustion, the Quartus Prime software exited the loop automatically.
ACTION: Check the loop for potential mistakes in the terminating conditions. If you intended for the loop to iterate more than the specified number of iterations, increase the limit using the VERILOG_CONSTANT_LOOP_LIMIT logic option.
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