List of Messages |
CAUSE: In a Verilog Design File (.v) at the specified location, you declared one or more objects with the specified type. In addition, you specified the object(s) as signed or unsigned. However, Quartus Prime Integrated Synthesis does not allow you to specify signed or unsigned when declaring objects with integer, real, time, or realtime types.
ACTION: Remove the signed or unsigned keyword from the object declaration or change the object declaration's type.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.