List of Messages |
CAUSE: In a Verilog Design File (.v) at the specified location, a binary number contains an illegal character.
ACTION: Make sure you use only 0 and 1 digits in binary numbers.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.