List of Messages |
always @ (posedge clk or posedge rst1 or posedge rst2) begin if ( rst1 || rst2 ) q <= 1'b0; else q <= d; endQuartus Prime Integrated Synthesis uses the if condition to identify the two asynchronous resets and, by implication, the clock. For edge classification, Quartus Prime Integrated Synthesis requires that a condition fall into one of two categories. It can refer to a single edge identifier (to match posedge events) or its complement (to match negedge events), for example, rst1, !rst1, rst1 == 1'b1, rst1 == 1'b0. It can also OR two or more expressions that each refer to a single edge identifier or its complement, for example, (rst1 || rst2), (!rst1 || !rst2). You can receive this error if your condition tests for the wrong polarity, or if it tests for the value of a variable that is not an edge in the event control. For example, to match a posedge rst event, the condition must be rst or rst = 1'b1. Finally, you can receive this error if you are attempting to use a single condition expression to test for both an asynchronous reset/set and a synchronous reset/set condition. The following code fragment contains an example of an illegal condition expression:
always @ (posedge clk or posedge rst) begin if ( rst || sync_rst ) q <= 1'b0; else q <= d; endQuartus Prime Integrated Synthesis generates this error message when compiling this design because it cannot match sync_rst to an edge on the sensitivity list.
always @ (posedge clk or posedge rst) begin if (rst1) q <= 1'b0; else if (sync_rst) q <= 1'b0; else q <= d; end
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