List of Messages |
CAUSE: In a Verilog Design File (.v) at the specified location, the specified octal constant value contains one or more illegal characters, that is, characters other than 0..7, x, or z.
ACTION: Make sure the octal constant value contains only 0..7, x, or z characters.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.