List of Messages |
CAUSE: In a Verilog Design File (.v) at the specified location, you instantiated an array of instances. However, Quartus Prime Integrated Synthesis cannot find the module declaration corresponding to the module you are instantiating. Because Verilog HDL connects ports on an array of instances differently depending on the formal port widths, Quartus Prime Integrated Synthesis must have previously analyzed the declaration for the instantiated module prior to elaborating this array of instances.
ACTION: Add the design file containing the declaration for the module to the list of files in your Quartus Prime project. If you are attempting to instantiate an Altera megafunction, an Altera primitive, or an entity written in another language, e.g. VHDL or AHDL, you must first create a suitable Verilog HDL wrapper; Quartus Prime Integrated Synthesis supports arrays of instances only when instantiating Verilog HDL modules.
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