List of Messages |
CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you connected the specified port on the specified instance more than once. That is, you connected the specified port more than once in the port map (VHDL) or port connection list (Verilog).
ACTION: Remove any duplicate connections for the specified port from the port map (VHDL) or the port connection list (Verilog).
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