List of Messages |
CAUSE: In a block declaration at the specified location SystemVerilog Design File (.sv), you used both a statement label and a block name. SystemVerilog does not allow these features to be used together.
ACTION: Remove the statement label and maintain the block name.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.