List of Messages |
CAUSE: In a module or interface declaration at the specified location in a SystemVerilog Design File (.sv), you declared an interface port with a specific modport access (the formal modport specification); however, when you instantiated the module or interface, you connected the port to an interface object with different modport access restrictions (the actual modport specification).
ACTION: Modify the declaration or the instantiation to make the modport access consistent.
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