List of Messages |
CAUSE: In a module instantiation at the specified location in a SystemVerilog Design File (.sv), you instantiated a module and connected its ports using one or more implicit port connections (.* or .name); however, Quartus Prime Integrated Synthesis could not resolve these port connections without the instantiated module's full declaration or an equivalent extern declaration. If you are instantiating an entity written in another language, you must create an extern module declaration that provides a suitable prototype for the entity in SystemVerilog.
ACTION: Add a file containing a declaration for the instantiated module to the project's file list.
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