List of Messages |
CAUSE: In a module instantiation at the specified location in a SystemVerilog Design File (.sv), you attempted to connect the specified port with an implicit port connection; however, the implicit port connection failed for the reason indicated in the specified text. To connect a module port with an implicit port connection, a compatible variable or port must be visible in the present scope. A variable or port is compatible if it has the same name as the module port and an equivalent type.
ACTION: If you intend to leave the module port unconnected, you must use an explicit port connection to the empty expression. Otherwise, make sure the present scope contains a variable or port with a compatible type.
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