List of Messages |
CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), the specified module or entity was declared with the synthesis_greybox attribute, indicating that the module or entity represents a greybox netlist, which should be used only by an external EDA synthesis tool. When compiling the design with Integrated Synthesis, you must use the actual module or entity.
ACTION: Remove the file containing the greybox netlist from your project, and include the file with the actual module or entity.
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