List of Messages |
CAUSE: In a Module Instantiation port connection in the Verilog Quartus Mapping File (.vqm) that you generated with another EDA tool, you used the logical negation operator (!) with the specified output port or specified bit-select or part-select of a declared vector net. However, you cannot use a logical negation operator with these type of ports. This error may also have occurred if you created or edited a VQM File manually.
wire temp; assign temp = !outThen change the Module Instantiation to example example1(in, temp). In general, it is better to correct the source design file rather than the VQM File, and then regenerate the VQM File. If the error persists, contact the EDA tool vendor support for more information.
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