List of Messages |
CAUSE: The specified Verilog Design File (.v) node instance is instantiated with the specified parameter, but should have the specified parameter name. The specified illegal parameter has a different case than the legal parameter name. Case mismatch in the parameter name is illegal when a Verilog module instantiates another Verilog submodule.
ACTION: Check the prototype of the entity and instantiate the entity with the correct parameter name.
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