List of Messages |
CAUSE: The specified partition in your design was imported from a QXP and contains the IP that requires a connection to the JTAG interface on the target device. For example, it may contain a Nios II processor with a JTAG Debug Module. Your design also has one or more partitions that support partial reconfiguration, or your design uses CvP. The Quartus Prime software does not support imported IP that requires a connection to the JTAG interface on the chip in designs that use partial reconfiguration or CvP.
ACTION: Compile the partition using the original HDL source, or do not use partial reconfiguration or CvP in your design.
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