ID:12137 Design file does not contain any entity that could be converted to Verilog/VHDL

CAUSE: You attempted to convert a Block Design/Schematic File (.bdf) to a Verilog/VHDL design file. The Block Design File, however, could not be converted to the appropriate Verilog/VHDL entity. This could be a result of the Block Design File name conflicting with Quartus Prime primitive names.

ACTION: Read any warnings/errors issued. Rename the Block Design File if it is conflicting with Quartus Prime primitive names.