List of Messages |
CAUSE: You attempted to convert a Block Design/Schematic File (.bdf) to a Verilog/VHDL design file. The Block Design File, however, could not be converted to the appropriate Verilog/VHDL entity. This could be a result of the Block Design File name conflicting with Quartus Prime primitive names.
ACTION: Read any warnings/errors issued. Rename the Block Design File if it is conflicting with Quartus Prime primitive names.
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