List of Messages |
CAUSE: The specified partition contains a signal or variable declared in the VHDL or System Verilog packages. However, bottom-up incremental compilation flow for the signal or variable declared in the VHDL or System Verilog packages is not supported in this version of the Quartus Prime software.
ACTION: No action is required.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.