List of Messages |
CAUSE: You used the --vector_source option but did not specify a VHDL Test Bench File (.vht). You must specify a Verilog Test Bench File or VHDL Test Bench File using the --testbench_file option if you use the --vector_source option.
ACTION: Specify a Verilog Test Bench File or VHDL Test Bench File to use with the --testbench_file option.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.