List of Messages |
CAUSE: The Synopsys PrimeTime timing analysis tool settings specify VHDL as the output format. However, the TimeQuest Timing Analyzer does not support VHDL format for Synopsys PrimeTime timing analysis tool in the current device family.
ACTION: If you want to use Synopsys PrimeTime timing analysis tool as the EDA timing analysis tool in the current device family, switch to Verilog format.
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