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module test (input in, oe, inout bidir, output out); assign out = bidir; assign out = oe ? in : 1'bZ; endmoduleIn the example, the first continuous assignment creates an illegal directional connection in between bidir to out. The assignment implies that data only flows from bidir to out. However, the assignment does not indicate a driving condition, so the Quartus Prime software interprets that bidir always drives the output pin. However, out also has a tri-state driver. As a result, a potential electrical conflict exists if the tri-state driver for out is active.
ACTION: Remove the directional connection from the design or specify a driving condition.
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