List of Messages |
CAUSE: The specified PLL is attempting to compensate for two or more LVDS clock trees. However, each PLL can compensate only for one LVDS clock tree.
ACTION: Relax the location constraints on the LVDS SERDES channels driven by the specified PLL, or make sure that the LVDS SERDES channels driven by the specified PLL are constrained to the same LVDS clock tree.
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