List of Messages |
CAUSE: You created a LATCH primitive is missing input, enable, or output signals. The Quartus Prime software cannot convert a LATCH primitive without properly connected input, enable, or output signals into a valid group of VHDL or Verilog statements.
ACTION: Make sure the necessary input, enable, and output signals are connected to the LATCH primitive and create the HDL design file again.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.