List of Messages |
CAUSE: You created a Graphic Design File (.gdf), but the specified flipflop primitive is missing one or more necessary input, output, or clock signals. The Quartus Prime software cannot convert a flipflop primitive without properly connected input, output, or clock signals into a valid group of VHDL or Verilog statements.
ACTION: Make sure the necessary data input, output, and clock signals are connected to the flipflop primitive and create the HDL design file again.
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