List of Messages
Parent topic: List of Messages

ID:186017 Transmitter clock output port drives <name> for fast PLL "<name>"

CAUSE: In the specified fast PLL, the SERDES transmitter clock output port drives the specified logic. The transmitter clock output port must drive only I/O pins.

ACTION: Modify the design so that the transmitter clock output port drives I/O pins.

Parent topic: List of Messages

Contact Altera | Legal Notice

Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.