| List of Messages | |
CAUSE: The specified number of DQS I/O pins referenced by the specified system clock pin in the design exceeds the specified maximum number of DQS I/O pins that can be placed on one side of the device.
ACTION: Modify the design to reduce the number of DQS I/O pins driven by the same system clock so that all DQS pins referenced by the clock can be placed on one side of the device.
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