List of Messages
Parent topic: List of Messages

ID:186510 coreclk input port (phase compensation FIFO read clock) of GXB receiver channel <name> in GIGE mode is sourced by node "<name>". The coreclk input should be fed by the coreclk output of the GXB transmitter PLL that feeds the write clock port of this receiver's phase compensation FIFO

CAUSE: The coreclk input port (phase compensation FIFO read clock) of the specified GXB receiver channel in GIGE mode is fed by the specified node. The coreclk input should be fed by the coreclk output of the GXB transmitter PLL that feeds the write clock port of this receiver's phase compensation FIFO.

ACTION: Modify the design so that the coreclk input port of the specified GXB receiver channel in GIGE mode is fed by the coreclk output of the GXB transmitter PLL that feeds the write clock port of this receiver's phase compensation FIFO.

Parent topic: List of Messages

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