List of Messages |
CAUSE: The coreclk input port (phase compensation FIFO read clock) of the specified GXB transmitter PLL that feeds the write clock port of this receiver's phase compensation FIFO.
ACTION: Modify the design so that the coreclk input port of the specified GXB receiver channel is fed by the coreclk output of the GXB transmitter PLL that feeds the write clock port of this receiver's phase compensation FIFO.
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