ID:186511 coreclk input port (phase compensation FIFO read clock) of GXB receiver channel "<name>" with channel width of <number> is sourced by node "<name>". Bytes may be reordered at the receive parallel interface (GXB receiver channel data outputs). The coreclk input should be fed by this receiver's clock output signal (which feeds the write clock port of this receiver's phase compensation FIFO). Contact Altera Applications for further information

CAUSE: The coreclk input port (phase compensation FIFO read clock) of the specified gigabit transceiver block (GXB) receiver channel is fed by the specified node. In this configuration, there is a possibility that bytes may be reordered at the receive parallel interface (GXB receiver channel data outputs). The coreclk input should be fed by the clock output signal of this receiver (which feeds the write clock port of this receiver's phase compensation FIFO).

ACTION: Modify the design so that the coreclk input port of the specified GXB receiver channel is fed by the clock output signal of this receiver. Contact Altera Applications for further information.