List of Messages
Parent topic: List of Messages

ID:186372 Can't place enhanced PLL "<name>" in PLL location <name> because PLL uses both EXTCLK and CLK0 output ports (therefore they share the same PLL G0 counter) but they are not controlled by the same clock enable signal

CAUSE: The specified enhanced PLL uses both EXTCLK and CLK0 output ports controlled by different clock enable signals. However, the Fitter cannot place the PLL in the specified PLL location because EXTCLK and CLK0 share the same PLL G0 counter at that PLL location, and therefore they must be controlled by the same clock enable signal.

ACTION: Use the same clock enable signal to control both EXTCLK and CLK0 output ports of the specified PLL, or assign the specified PLL to a different enhanced PLL location.

Parent topic: List of Messages

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