List of Messages
Parent topic: List of Messages

ID:186236 External clock ports of enhanced PLL "<name>" are driving <number> pairs of output pins -- they must not feed more than four pairs of output pins

CAUSE: The external clock ports of the specified enhanced PLL drive more than four pairs of output pins. However, the enhanced PLL must not feed more than four pairs of output pins.

ACTION: Modify the design so the enhanced PLL feeds no more than four pairs of output pins.

Parent topic: List of Messages

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