List of Messages
Parent topic: List of Messages

ID:186246 Output clock clk<port number> of enhanced PLL "<name>" drives both regional and global clocks

CAUSE: The Fitter cannot place the specified enhanced PLL because the specified output clock requires both regional and global clocks, but the output clock of the enhanced PLL cannot drive both regional and global clocks. This error often occurs if you assign the Global Signal logic option to the output clock.

ACTION: Modify the design so that the output clock of the PLL drives either regional or global clocks, or delete the Global Signal logic option for the output clock.

Parent topic: List of Messages

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