ID:186273 Fast or enhanced PLL clock output port <name> has illegal Global Signal logic option setting (<type>) -- must be set to Global Clock or Regional Clock

CAUSE: You assigned an illegal Global Signal logic option setting for the specified clock output port of a fast PLL or enhanced PLL. The PLL clock output port can only accept Global Clock or Regional Clock settings as Global Signal assignments.

ACTION: Delete or change the Global Signal logic option setting for the PLL clock output port.