List of Messages
Parent topic: List of Messages

ID:186054 All differential I/O SERDES receivers that are driven by fast PLL "<name>" have CORE_CLK input frequency of <number> MHz, but frequency must be <number> MHz

CAUSE: All differential I/O SERDES receivers that are driven by the specified fast PLL have the specified CORE_CLK input frequency, but must have the specified required CORE_CLK input frequency.

ACTION: Modify the design so that all differential I/O SERDES receivers that are driven by the fast PLL have the required CORE_CLK input frequency.

Parent topic: List of Messages

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