List of Messages |
CAUSE: Double data rate (DDR) pin group has registers feeding the specified DQS I/O and its associated DQ I/O pins that are not driven by the same PLL, but registers must be clocked by the same PLL.
ACTION: Modify the design so that the same PLL is used to generate the clocks of the registers feeding the DQS and DQ I/O pins in the DDR pin group.
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