ID:186410 DDR pin group must have registers feeding DQS I/O pin "<name>" and its associated DQ I/O pins that are clocked by same PLL

CAUSE: Double data rate (DDR) pin group has registers feeding the specified DQS I/O and its associated DQ I/O pins that are not driven by the same PLL, but registers must be clocked by the same PLL.

ACTION: Modify the design so that the same PLL is used to generate the clocks of the registers feeding the DQS and DQ I/O pins in the DDR pin group.