| List of Messages | |
CAUSE: You created a double data rate (DDR) pin group that consists of a clock, a PLL, and a DQS I/O pin and its DQ I/O pins. You made location assignments for the members of the DDR pin group that are all referenced by the specified system clock. However, the Fitter cannot place the members of the group in the assigned location and meet the DQS I/O pin placement requirement.
ACTION: Change location assignments for the clock, the PLL, or the DQS I/O pin and its DQ I/O pins to ensure that the locations are compatible on the device.
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